A Scalable Pipeline Architecture for Line Rate Packet Classification on Fpgas

Multi-dimensional packet classification is a key function for networking applications in high-speed routers. Although a multitude of research has explored this area, efficient packet classification that supports large rule sets at line rate remains challenging. This paper presents a scalable pipeline architecture, named BiConOLP, for line rate packet classification on FPGAs. We study the problem of balancing memory distribution across pipeline stages while keeping overall resource usage low using a multitude of pre and post mapping waste elimination techniques, algorithm optimizations, and customized hardware implementations. Our experimental results show that our architecture can store 10K unique, 5-field rules in a single Xilinx Virtex5 FPGA. Our architecture can also sustain above 45 Gbps throughput for minimum size (40 bytes) packets with only 45.6% memory resource usage, making our design competitive with many state-of-the-art FPGA-based packet classification engines. To the best of our knowledge, our work is the first to achieve perfectly balanced memory distribution (to within 10% overall) over both decision tree and rule list pipeline stages and support large rule sets at line rate with efficient resource utilization.